SymbolicLight V2 combines sparse event computation with continuous-state processing. The architecture extends V1’s spike-gated dual paths with graded signed events and local attention. The 194M-parameter model was implemented on an Alveo U50C FPGA using digital fixed-point arithmetic, achieving a decode throughput of 643.2 tokens/s for a 32-token prefix and 128 outputs. Across three FPGA implementations, active-row weight gathering and valid-state KV loading improved throughput. Complete-request energy fell by 24.4-27.7% across three prefix lengths.
On a ROCK 5T with Cortex-A76 cores, complete requests reached 65.4 tokens/s at 9.80 W and 0.151 J per generated token. The results connect event sparsity to omitted computation and data movement. The architecture supports other dedicated V2 implementations, increasing throughput while lowering energy per generated token.
Evaluation holds the deployed checkpoint fixed and does not establish equal-quality efficiency compared to a dense control. The reduction in estimated card energy during short-context decode using integer FPGA execution is 89.1% compared to a RTX 5090 baseline.
Source: https://arxiv.org/abs/2609.09772